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2025-06-09 - 09:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8.osadl.org (updated Sun Jun 08, 2025 12:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
131176996611,653cyclictest391755-21meminfo11:50:2611
131183994510,450cyclictest378051-21meminfo11:35:2115
131181994330,431cyclictest387031-21meminfo11:45:2214
131184991090,107cyclictest136145-21meminfo07:15:002
131186991060,104cyclictest203794-21meminfo08:25:224
131187991030,102cyclictest251589-21meminfo09:15:225
131183998232,26cyclictest3232022-21Isolated15:05:2315
131179998174,5cyclictest0-21swapper/712:04:1513
13118699790,78cyclictest283603-21meminfo09:50:194
13118499780,77cyclictest401816-21meminfo12:00:212
131189997772,1cyclictest0-21swapper/1511:57:517
13118399770,76cyclictest382601-21meminfo11:40:2015
13117299760,75cyclictest317689-21meminfo10:30:161
13118599750,74cyclictest162251-21meminfo07:40:203
13118599750,74cyclictest162251-21meminfo07:40:203
13118499750,74cyclictest242116-21meminfo09:05:202
13117199740,73cyclictest340562-21meminfo10:55:180
131187997362,3cyclictest3451421-21Isolated15:05:235
13118599730,71cyclictest166685-21meminfo07:45:233
13117499730,71cyclictest372708-21meminfo11:30:189
13118699720,71cyclictest247141-21meminfo09:10:214
13118499720,71cyclictest133628-21meminfo07:10:182
13118499710,70cyclictest322114-21meminfo10:35:182
13118199710,69cyclictest232970-21meminfo08:55:2014
13117499710,70cyclictest425310-21meminfo12:25:209
13117299710,70cyclictest279165-21meminfo09:45:211
13118799700,69cyclictest218595-21meminfo08:40:235
131174997047,11cyclictest3829503-21AppRun12:02:369
13117499700,69cyclictest194216-21meminfo08:15:219
13117399690,68cyclictest406558-21meminfo12:05:218
13118799680,67cyclictest213696-21meminfo08:35:205
13118599680,67cyclictest270243-21meminfo09:35:213
13118599680,67cyclictest256022-21meminfo09:20:213
13118499680,66cyclictest354058-21meminfo11:10:192
13117699680,67cyclictest213697-21meminfo08:35:2111
13117399680,67cyclictest322113-21meminfo10:35:188
13117299680,67cyclictest335410-21meminfo10:50:191
13117199680,67cyclictest139190-21meminfo07:15:230
13118799670,66cyclictest411208-21meminfo12:10:215
13118799670,66cyclictest411208-21meminfo12:10:215
13118399670,66cyclictest143606-21meminfo07:20:2315
13117999670,66cyclictest368090-21meminfo11:25:1813
13117999670,66cyclictest358507-21meminfo11:15:2113
13117599670,66cyclictest387030-21meminfo11:45:2210
13117599670,66cyclictest302318-21meminfo10:10:2310
13117499670,66cyclictest411210-21meminfo12:10:229
13117499670,66cyclictest411210-21meminfo12:10:229
13117399670,66cyclictest349599-21meminfo11:05:208
13117399670,66cyclictest302316-21meminfo10:10:228
13117399670,66cyclictest218594-21meminfo08:40:238
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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