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2025-06-18 - 03:56
OSADL QA Farm

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of system in rack #3, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot4.osadl.org (updated Wed Jun 18, 2025 00:47:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)		T*(,W**)
latency
(µs)		CmdPIDPrioCmd
3778947222562243,6sleep33774816-21kworker/3:4+events@
dbs_work_handler		19:09:273
3778947222562243,6sleep33774816-21kworker/3:4+events@
dbs_work_handler		19:09:263
37776882182162,8sleep23776868-21kworker/2:0+events@
dbs_work_handler		19:05:232
37776882182162,8sleep23776868-21kworker/2:0+events@
dbs_work_handler		19:05:232
37791999911460,20cyclictest64250irq/527-eth0-Tx21:00:290
37791999911460,20cyclictest64250irq/527-eth0-Tx21:00:290
37792319911096,7cyclictest3885678-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		22:07:343
37791999910563,25cyclictest0-21swapper/000:30:390
37791999910563,25cyclictest0-21swapper/000:30:380
377919999992,59cyclictest3843980-21/usr/sbin/munin21:25:440
3779199999758,28cyclictest64350irq/528-eth0-Tx19:20:010
377919999972,56cyclictest3959049-21ls23:00:010
40584262950,6chrt0-21swapper/200:22:192
40584262950,6chrt0-21swapper/200:22:182
377919999953,86cyclictest0-21swapper/020:10:250
377919999953,86cyclictest0-21swapper/020:10:250
39367752930,4sleep20-21swapper/222:41:192
39367752930,4sleep20-21swapper/222:41:182
377919999939,30cyclictest0-21swapper/023:31:160
377919999939,30cyclictest0-21swapper/023:31:150
3779199999331,18cyclictest64350irq/528-eth0-Tx21:45:320
3779231999078,6cyclictest3842813-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		21:57:333
3779199999034,7cyclictest64450irq/529-eth0-Tx23:55:200
377919999902,56cyclictest0-21swapper/019:45:290
377919999891,79cyclictest0-21swapper/021:38:510
3779199998854,4cyclictest0-21swapper/021:20:410
3779199998839,14cyclictest0-21swapper/022:21:180
3779199998839,14cyclictest0-21swapper/022:21:180
3779199998638,14cyclictest64450irq/529-eth0-Tx20:45:010
3779199998550,5cyclictest64250irq/527-eth0-Tx22:45:040
3779199998529,4cyclictest64350irq/528-eth0-Tx00:00:190
3779199998529,4cyclictest64350irq/528-eth0-Tx00:00:180
377738628559,16sleep40-21swapper/419:05:194
377738628559,16sleep40-21swapper/419:05:184
3779199998427,46cyclictest3842813-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		21:58:280
377919999841,5cyclictest1165-21runrttasks00:13:200
377919999841,56cyclictest0-21swapper/020:16:130
3779211998370,6cyclictest4023006-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		00:03:001
3779211998370,6cyclictest4023006-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		00:03:001
377919999834,36cyclictest3827114-21diskmemload21:50:370
377919999834,36cyclictest3827114-21diskmemload21:50:360
3779199998327,17cyclictest0-21swapper/000:17:590
3779252998275,3cyclictest0-21swapper/519:12:105
3779231998269,7cyclictest4013725-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		23:52:573
3779199998258,17cyclictest3821031-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		21:07:250
3779199998258,17cyclictest3788977-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		20:02:160
3779199998250,4cyclictest64350irq/528-eth0-Tx19:55:330
3779199998244,4cyclictest64550irq/530-eth0-Tx23:50:380
3779220998169,6cyclictest3811230-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		20:42:222
39150442800,6sleep30-21swapper/322:23:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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