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2025-05-17 - 03:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Sat May 17, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1018299114296041,5384cyclictest22709-21kworker/0:019:57:260
101829999015269,4621cyclictest2892-21kworker/0:221:24:330
101829998805263,4612cyclictest2892-21kworker/0:222:07:430
101829998545046,4798cyclictest2892-21kworker/0:222:23:590
101829998055227,4567cyclictest22709-21kworker/0:019:27:300
101829994424865,4573cyclictest8523-21kworker/0:122:55:490
101829993644820,4534cyclictest2892-21kworker/0:222:11:430
101829993214679,4627cyclictest15322-21kworker/0:023:07:160
101829993164794,4512cyclictest2892-21kworker/0:221:56:040
101829990884661,4422cyclictest31609-21kworker/0:200:07:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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