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2025-05-14 - 23:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Wed May 14, 2025 12:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050650,0irq/25-eth00-21swapper/107:05:151
110050600,0irq/25-eth00-21swapper/207:08:352
117950590,0irq/26-eth1-rx-0-21swapper/307:07:213
9950540,0irq/24-0000:00:0-21swapper/007:05:250
351180,0ktimersoftd/327453-21cp09:51:273
271180,0ktimersoftd/227440-21sshd09:51:272
20377991817,0cyclictest10939-21sshd12:14:572
20377991817,0cyclictest10939-21sshd12:14:572
2037699180,0cyclictest20150-21smartctl11:55:221
2037699180,0cyclictest20150-21smartctl11:55:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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