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2025-07-03 - 22:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackaslot0.osadl.org (updated Thu Jul 03, 2025 12:44:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
195532600,0sleep10-21swapper/110:30:491
1568026024,19sleep00-21swapper/007:06:010
275422590,1sleep127545-21cpuspeed_turbos08:40:171
87212540,0sleep30-21swapper/312:05:053
116852540,0sleep00-21swapper/011:04:140
26282530,1sleep02625-21sshd11:53:560
130702530,0sleep228-21rcuc/209:46:032
317582520,1sleep331754-21sshd10:32:153
256682510,1sleep21722-21runrttasks12:25:142
243032510,1sleep024297-21sshd12:34:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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