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2025-05-14 - 16:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Wed May 14, 2025 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
70012234166,23sleep20-21swapper/207:09:372
70102207167,22sleep10-21swapper/107:09:441
69252204169,23sleep00-21swapper/007:08:390
67592204171,21sleep30-21swapper/307:06:293
766521510,6sleep3732699cyclictest09:20:153
49412710,5sleep0732399cyclictest12:35:010
732399602,17cyclictest28610-21cat08:55:200
732399542,11cyclictest16381-21cut09:35:250
249472540,2sleep20-21swapper/208:50:022
732399533,10cyclictest28798-21cat12:15:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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