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2025-05-14 - 20:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Wed May 14, 2025 12:46:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1991574997721,37cyclictest2019923-21kworker/u32:4+events_unbound08:00:164
199157499750,56cyclictest2042685-21kworker/u32:5+events_unbound09:03:174
1991574997435,39cyclictest2103914-21chrt10:26:044
199157499740,55cyclictest2048281-21kworker/u32:1+events_unbound08:59:064
199157499740,55cyclictest2042685-21kworker/u32:5+events_unbound08:50:414
1991574997233,39cyclictest0-21swapper/411:49:494
1991574997233,39cyclictest0-21swapper/411:49:484
1991574997233,19cyclictest0-21swapper/412:09:364
1991574997132,39cyclictest0-21swapper/410:06:284
1991574997112,40cyclictest2002387-21taskset07:26:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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