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2025-05-13 - 21:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue May 13, 2025 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7262982315280,20sleep10-21swapper/107:07:231
7264172258188,56sleep00-21swapper/007:08:420
72669399155149,4cyclictest793099-21kworker/u8:209:49:211
87657021450,5sleep10-21swapper/111:24:211
8906022800,6sleep00-21swapper/011:42:500
125899700,6rtkit-daemon1257-21rtkit-daemon12:15:271
7447412690,5sleep1141rcu_preempt07:50:251
125899590,4rtkit-daemon1257-21rtkit-daemon10:51:241
125899590,3rtkit-daemon1257-21rtkit-daemon09:15:250
125899580,4rtkit-daemon1257-21rtkit-daemon09:23:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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